Low Leakage SRAM Memory
50,30 €*
Sofort verfügbar, Lieferzeit: 1-3 Tage
Produktnummer:
9786205517116
I present some techniques to decrease the gate and other leakage dissipation in Deep Sub-Micron SRAM memories. This book reviews detail SRAM operations. This book also reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Finally, the book explores different circuit techniques to reduce the leakage power consumption. The W/L ratios are calculated from the equations of current in transistors (Linear and Saturation mode) for smooth read-write operation of both 0 and 1. I use W1/W3 = 1.5 and W4/W6 = 1.5. I first designed conventional SRAM memory and observed leakage current in various technology. In 90 nm technology conventional SRAM shows a leakage current of 1.87nA at steady state. Data retention gated-ground cache (DGR-cache) method reduces the leakage current to 100pA. Drowsy cache method reduces the leakage current to 84pA.
| Autor: | Mukherjee, Debasis |
|---|---|
| EAN: | 9786205517116 |
| Sprache: | Englisch Deutsch |
| Seitenzahl: | 68 |
| Produktart: | kartoniert, broschiert |
| Verlag: | LAP Lambert Academic Publishing |
| Untertitel: | Design of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique. DE |
| Schlagworte: | VLSI Nachrichtentechnik Electronics Leakage SRAM |
| Größe: | 150 × 220 |
