High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
120,00 €*
Sofort verfügbar, Lieferzeit: 1-3 Tage
Produktnummer:
9789811093210
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
| Autor: | Chattopadhyay, Anupam Wang, Zheng |
|---|---|
| EAN: | 9789811093210 |
| Sprache: | Englisch |
| Seitenzahl: | 220 |
| Produktart: | kartoniert, broschiert |
| Verlag: | Springer Nature Singapore Springer Singapore |
| Veröffentlichungsdatum: | 12.05.2018 |
| Größe: | 13 × 155 × 235 |
| Gewicht: | 341 g |
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
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